Voltage regulators involve high speed switching. Thus electrostatic discharge (ESD) protection using a local clamp approach for protecting such voltage regulators presents a challenge since the switching time of the regulator during normal operation is 10 ns-200 ps and is comparable to and may be significantly lower than the ESD pulse rise time (10 ns for Human Body Model (HBM) pulse).
Typically local protection ESD protection cells or devices are designed to trigger before their voltage breakdown level is reached. This is called the dV/dt effect and is the result of device turn-on due to early triggering rather than due to breakdown voltage being reached. In fact, in the case of high voltage devices the dV/dt effect becomes the major consideration in ESD device design since there is not much blocking junction to choose from.
A common local clamp ESD protection approach is based on SCR snapback devices. In particular, to avoid additional process steps in BiCMOS and BCD processes, the SCR devices are commonly based on NPN BJT and NLDMOS based SCR devices. A typical NPN BJT is shown in FIG. 1 and an ESD device based on an NPN BJT structure, referred to as a bipolar SCR (BSCR) is shown in FIG. 2. Similarly, FIG. 3 shows a typical NLDMOS, while an SCR device based on the NLDMOS structure (referred to as an LDMOS-SCR) is shown in FIG. 4. In each case the SCR device is formed by embedding an additional parasitic PNP structure by means of an additional p-emitter region as is discussed in greater detail below.
The NPN BJT 100 of FIG. 1 includes an emitter 102 formed on top of a p-base 104 and an n-collector 106 with its sub-collector region in the form of an n-sinker 108 and an n-buried layer (NBL) 110 formed in an n-epitaxial region 112. For ease of comparison, the corresponding regions in the BSCR 200 have made use of the same numbering. As shown in FIG. 2, the BSCR 200 provides a pnpn structure by including an extra p− region 202 (also referred to as the p-SCR-emitter region 202) separated from the n+ collector 106 by a shallow trench isolation region (STI) 204 and from the p-base 104 by a second STI region 206. The extra p-region region 202 defines a parasitic PNP structure with the n-regions of the n-sinker, NBL 110 and n-epitaxial region 112, and with the p-region of the p-base 104.
In order to achieve high voltage tolerance at submicron dimension the blocking junction electrodes (contact 220 to collector 106 and contact 224 to base 104) in the ESD device are shorted to the corresponding p-SCR-emitter 202 and cathode emitter 102. This is best understood with respect to the equivalent circuit diagram of FIG. 5. The collector contact 220, which defines the blocking junction connection, is connected to the p-SCR-emitter contact 222, which is in turn connected to the pad to define the anode, while the p-base contact 224 which controls a second blocking junction is connected to the emitter connector 226, the base contact 224 and emitter contact 226 being connected to ground and defining the cathode. The equivalent circuit of FIG. 5, which shows the internal resistance of the drift blocking junction regions as rC and rB.
The NLDMOS 300, is shown in FIG. 3. It includes an n+ drain 302 formed in an n-well 304, and an n+ source 306 formed in a p-well or p-body 308. In order to provide a bulk contact 310 to the p-body or p-well 308, a p+ region 312 is formed in the p-well 308. As shown in FIG. 3, the source contact 314, which forms the cathode, is connected to the bulk contact 310, and both are connected to ground. The drain contact 316, in turn, forms the anode and is connected to the pad. A gate 320 is formed over the channel region between the drain and the source and is separated from the n+ drain 302 by a shallow trench isolation (STI) region 321. As shown, the n-well 304 and p-well 308 are formed in an n-epitaxial layer 322 with an NBL 324 below the epitaxial layer 322.
The NLDMOS-SCR 400 of FIG. 4 is similar to the NLDMOS 300 and corresponding regions are therefore depicted by the same reference numerals. The NLDMOS-SCR differs in that an additional p+ region 402 is formed in the n-well 304. In the embodiment shown, the p+ emitter region 402 is formed on the gate side adjacent the n+ drain 302. A floating n+ region 404 is formed on the gate to side of the p+ region 402 to provide proper junction isolation, and is separated from the gate 320 by a shallow trench isolation region 410.
It will be appreciated that the additional p+ region 402 (also referred to as the p-SCR-emitter) defines a parasitic PNP transistor with the n-well 304 and p-well 308 with its p+ bulk contact region 312. The p+ region 402 also provides for the SCR's pnpn configuration as defined by the p+ region 402, the n-region (as defined by the n-well 304, the n-epi 322, and the NBL 324), the p-well 308, and the n+ source region
In order to achieve high voltage tolerance at submicron dimension the respective blocking junction electrodes in the ESD device (contact 316 to n+ drain 302 and p+ bulk contact 310 to bulk contact region 312) are shorted to the corresponding p-SCR-emitter and cathode source as is also evident from the equivalent circuit diagram of FIG. 6. As shown, the drain contact 316, which defines the blocking junction connection, is connected to the p-SCR-emitter contact 412, which is connected to the pad to define the anode, while the bulk connector 310 which defines a second blocking junction is connected to the source connector 314, the bulk connector and source connector being connected to ground and defining the cathode. This is best understood with respect to the equivalent circuit of FIG. 6, which shows the internal resistance of the drift blocking junction regions as rD and rB.